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cy25403/cy25423/cy25483 three pll programmable clock generator with spread spectrum cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-12564 rev. *e revised june 02, 2010 features three fully integrated phase locked loops (plls) input frequency range ? external crystal: 8 to 48 mhz ? external reference: 8 to 166 mhz clock reference clock input voltage range ? 2.5 v, 3.0 v, and 3.3 v for cy25483 ? 1.8 v for cy25403 and cy25423 wide operating out put frequency range ? 3 to 166 mhz programmable spread spectrum with center and down spread option and lexmark and linear modulation profiles v dd supply voltage options: ? 2.5 v, 3.0 v, and 3.3 v for cy25403 and cy25483 ? 1.8 v for cy25423 selectable output clock voltages independent of v dd supply: ? 2.5 v, 3.0 v, and 3.3 v for cy25403 and cy25483 ? 1.8 v for cy25423 frequency select feature with optio n to select four different frequencies power down, output enable, and ss on/off controls low jitter, high accuracy outputs ability to synthesize nonstandard frequencies with fractional-n capability three clock outputs with programmable drive strength glitch-free outputs while frequency switching 8-pin soic package commercial and industrial temperature ranges benefits multiple high performance plls allow synthesis of unrelated frequencies nonvolatile programming for personalization of pll frequencies, spread spectrum char acteristics, drive strength, crystal load capacitance, and output frequencies application specific program mable emi reduction using spread spectrum for clocks programmable plls for system frequency margin tests meets critical timing requirem ents in complex system designs suitability for pc, consumer, portable, and networking applications capable of zero ppm frequency synthesis error uninterrupted system operation during clock frequency switch application compatibility in standard and lo w power systems block diagram osc pll1 pll3 (ss) clk3 (ss) clk2 (no ss ) clk1 (ss) crossbar switch fs1 sson xout xin/ exclkin pd#/oe pll 2 (ss) fs0 mux and control logic output dividers and drive strength control [+] feedback
cy25403/cy25423/cy25483 document #: 001-12564 rev. *e page 2 of 12 table 1. device selector guide figure 1. pin diagram - cy25403 8-pin soic table 2. pin definition - cy25403 (2.5 v, 3.0 v, or 3.3 v supply) device crystal input excklkin input v dd cy25403 yes 1.8v lvcmos 2.5v, 3.0v, 3.3v cy25483 no 2.5 v, 3.0 v, 3.3 v lvcmos 2.5 v, 3.0 v, 3.3 v cy25423 yes 1.8 v lvcmos 1.8 v pin number name io description 1 xin/exclkin input crystal input or 1.8 v external clock input 2v dd power power supply: 2.5 v, 3.0 v, or 3.3 v 3 clk1 output programmable clock output with spread spectrum 4 clk2/fs0 output/input multifuncti on programmable pin: programmable clock output with no spread spectrum or frequency select pin 5 pd#/oe/fs1 input multifunction programmable pin: po wer down, output enable or frequency select pin 6 clk3/sson output/input multifunction programmable pin: programmable clock output with spread spectrum or spread spectrum on/off control pin 7 gnd power power supply ground 8 xout output crystal output v dd cy25403 1 2 3 4 8 7 6 5 xout gnd clk3/sson pd#/oe/fs1 xin/ exclkin clk1 clk2/fs0 [+] feedback
cy25403/cy25423/cy25483 document #: 001-12564 rev. *e page 3 of 12 figure 2. pin diagram - cy25483 8-pin soic table 3. pin definition - cy25483 (2.5 v, 3.0 v, or 3.3 v supply) figure 3. pin diagram - cy25423 8-pin soic table 4. pin definition - cy25423 (1.8 v supply) pin number name io description 1 exclkin input 2.5 v, 3.0 v, or 3.3 v external clock input 2v dd power power supply: 2.5 v, 3.0 v, or 3.3 v 3 clk1 output programmable clock output with spread spectrum 4 clk2/fs0 output/input mult ifunction programmable pin: progra mmable clock output with no spread spectrum or frequency select pin 5 pd#/oe/fs1 input multifunction programmable pin: po wer down, output enable or frequency select pin 6 clk3/sson output/input multif unction programmable pin: programmabl e clock output with spread spectrum or spread spectrum on/off control pin 7 gnd power power supply ground 8 dnu output do not use this pin pin number name io description 1 xin/exclkin input crystal input or 1.8 v external clock input 2v dd power power supply: 1.8 v 3 clk1 output programmable clock output with spread spectrum 4 clk2/fs0 output/input multifunction programmable pin: programmable clock output with no spread spectrum or frequency select pin 5 pd#/oe/fs1 input multifunction programmable pin: power down, output enable or frequency select pin 6 clk3/sson output/input multifunction programmab le pin: programmable clock output with spread spectrum or spread spec trum on/off control pin 7 gnd power power supply ground 8 xout output crystal output v dd cy25483 1 2 3 4 8 7 6 5 dnu gnd pd#/oe/fs1 exclkin clk1 clk2/fs0 clk3/sson cy25423 1 2 3 4 8 7 6 5 xout gnd pd#/oe/fs1 xin/ exclkin v dd clk1 clk2/fs0 clk3/sson [+] feedback
cy25403/cy25423/cy25483 document #: 001-12564 rev. *e page 4 of 12 general description 3 configurable plls the cy25403, cy25423, and cy25483 have three programmable plls that can be used to generate output frequencies ranging from 3 to 166 mhz. the advantage of having three plls is that a single device generates up to three independent frequencies from a single crystal. input reference clocks the input reference clock can be either a crystal or a clock signal, for cy25403 and cy25423 while just a clock signal for cy25483. the input frequency range for crystal (xin) is 8 mhz to 48 mhz and that for external reference clock (exclkin) is 8 mhz to 166 mhz. the voltage range of the reference clock input for cy25483 is 2.5 v/3.0 v/3.3 v while that for cy25403 and cy25423 is 1.8 v. this gives user an option for this device to be compatible for different input clock vo ltage levels in the system. v dd power supply options these devices have programmable power supply options. the cy25403/cy25483 is a high voltage part that can be programmed to operate at any volt age 2.5 v, 3.0 v, or 3.3 v while cy25423 is a low voltage part that can operate at 1.8 v. output source selection these devices have programmable input sources for each of its clock outputs. there are four available clock sources and these clock sources are: xin/exclkin, pll1, pll2, and pll3. output clock source selection is done by using four out of four crossbar switch. thus, any one of these four available clock sources can be arbitrarily sele cted for the clock outputs. this gives user a flexibility to have up to three independent clock outputs. spread spectrum control two of the three plls (pll2 and pll3) have spread spectrum capability for emi reduction in the system. the device uses a cypress proprietary pll and spread spectrum clock (ssc) technology to synthesize and modulate the frequency of the pll. the spread spectrum feature can be turned on or off using a multifunction control pin (clk3/sson). it can be programmed to either center spread range from 0.125% to 2.50% or down spread range from ?0.25% to ?5.0% with lexmark or linear profile. frequency select each pll can be programmed for up to four different frequencies. there are two multifunction programmable pins, clk2/fs0 and pd#/oe/fs1 which if programmed as frequency select inputs, can be used to select among these arbitrarily programmed frequency settings. each output has programmable output divider options. glitch-free frequency switch when the frequency select pin, fs(1:0) is used to switch frequency, the outputs are g litch-free provided frequency is switched using output divi ders. this feature enables uninterrupted system operation while clock frequency is being switched. pd#/oe mode multifunction pin pd#/oe/fs1 (pin 5) can be programmed to operate as either frequency se lect (fs1), power down (pd#) or output enable (oe) mode. pd# is a low-true input. if activated it shuts off the entire chip, resulting in minimum power consumption for the device. setting this signal high brings the device in the operational mode with default register settings. when this pin is programmed as output enable (oe), clock outputs can be enabled or disabled using oe (pin 5). individual clock outputs can be programmed to be sensitive to this oe pin. output drive strength the dc drive strength of the individual clock output can be programmed for different values. ta b l e 5 shows the typical rise and fall times for different drive strength settings. generic configuration and custom frequency there is a generic set of output frequencies available from the factory that can be used for the device evaluation purposes. the device, cy25403, cy25423, and cy25483 can be custom programmed to any desired frequ encies and listed features. for customer specific programming, please contact local cypress field application engineer (fae) or sales representative. table 5. output drive strength output drive strength rise/fall time (ns) (typical value) low 6.8 mid low 3.4 mid high 2.0 high 1.0 [+] feedback
cy25403/cy25423/cy25483 document #: 001-12564 rev. *e page 5 of 12 absolute maximum conditions parameter description condition min max unit v dd supply voltage for cy25403/cy25483 ?0.5 4.5 v v dd supply voltage for cy25423 ?0.5 2.6 v v in input voltage for cy25403/cy25483 relative to v ss ?0.5 v dd +0.5 v v in input voltage for cy25423 relative to v ss ?0.5 2.2 v t s temperature, storage non functional ?65 +150 c esd hbm esd protection (human body model ) jedec eia/jesd22-a114-e 2000 volts ul-94 flammability rating v-0 at 1/8 in. 10 ppm msl moisture sensitivity level soic package 3 recommended oper ating conditions parameter description min typ max unit v dd v dd operating voltage for cy25403 2.25 ? 3.60 v v dd v dd operating voltage for cy25423 1.65 1.8 1.95 v t ac commercial ambient temperature 0 ? +70 c t ai industrial ambient temperature ?40 -- +85 c c load maximum load capacitance ? ? 15 pf t pu power up time for all v dd to reach minimum specified voltage (power ramps must be monotonic) 0.05 ? 500 ms [+] feedback
cy25403/cy25423/cy25483 document #: 001-12564 rev. *e page 6 of 12 dc electrical specifications parameter description conditions min typ max unit v ol output low voltage i ol = 2 ma, drive strength = [00] ? ? 0.4 v i ol = 3 ma, drive strength = [01] i ol = 7 ma, drive strength = [10] i ol = 12 ma, drive strength = [11] v oh output high voltage i oh = ?2 ma, drive strength = [00] v dd - 0.4 ? ? v i oh = ?3 ma, drive strength = [01] i oh = ?7 ma, drive strength = [10] i oh = ?12 ma, drive strength = [11] v il1 input low voltage of pd#/oe, fs0, fs1 and sson ? ? 0.2*v dd v v il2 input low voltage of exclkin ? ? 0.18 v v ih1 input high voltage of pd#/oe, fs0, fs1 and sson 0.8*v dd ??v v ih2 input high voltage of exclkin for cy25403/cy25423 1.62 ? 2.2 v v ih3 input high voltage of exclkin for cy25483 0.8*v dd ??v i il input low current, pd#/oe/fs1 v in = 0v ? ? 10 a i ih input high current, pd#/oe/fs1 v in = v dd ??10a i ildn input low current, sson and fs0 pins v in = 0v (internal pull down resistor = 160k typ.) ??10a i ihdn input high current, sson and fs0 pins v in = v dd (internal pull down resistor = 160k typ.) 14 ? 36 a r dn pull down resistor of clk1, clk2/fs0 and clk3/sson pins output clocks in off state by setting pd# = low 100 160 250 k i dd [ 1 , 2 ] supply current for cy25423 pd# = high, no load ?20?ma supply current for cy25403/cy25483 pd# = high, no load ?22?ma i dds [1] standby current pd# = low ?3?a c in [1] input capacitance sson, pd#/oe/ fs1 and fs0 pins ??7pf 1. guaranteed by design but not 100% tested. 2. configuration dependent. [+] feedback
cy25403/cy25423/cy25483 document #: 001-12564 rev. *e page 7 of 12 ac electrical specifications parameter description conditions min typ max unit f in (crystal) crystal frequency, xin 8 ? 48 mhz f in (clock) input clock frequency (exclkin) 8 ? 166 mhz f clk output clock frequency 3 ? 166 mhz dc output duty cycle, all clocks except ref out duty cycle is defined in figure 5 on page 8 ; t 1 /t 2 , measured at 50% of v dd 45 50 55 % dc ref out duty cycle ref in min 45%, max 55% 40 ? 60 % t rf1 [1] output rise/fall time measured from 20% to 80% of v dd, as shown in figure 6 on page 8 , cl = 15 pf, drive strength [00] ?6.8?ns t rf2 [1] output rise/fall time measured from 20% to 80% of v dd , as shown in figure 6 on page 8 , cl = 15 pf, drive strength [01] ?3.4?ns t rf3 [1] output rise/fall time measured from 20% to 80% of v dd , as shown in figure 6 on page 8 , cl = 15 pf, drive strength [10] ?2.0?ns t rf4 [1] output rise/fall time measured from 20% to 80% of v dd , as shown in figure 6 on page 8 , cl = 15 pf, drive strength [11] ?1.0?ns t ccj [1,2] cycle-to-cycle jitter (peak) configuration dependent. see table 6 ? 100 ? ps t lock [1] pll lock time measured from 90% of the applied power supply level ?13ms 1. guaranteed by design but not 100% tested. 2. configuration dependent. table 6. configuration example for c-c jitter ref. frequency (mhz) clk1 output clk2 output clk3 output freq. (mhz) c-c jitter typ (ps) freq. (mhz) c-c jitter typ (ps) freq. (mhz) c-c jitter typ (ps) 14.3181 8.0 134 166 103 48 92 19.2 74.25 99 166 94 8 91 27 48 67 27 109 166 103 48 48 93 27 123 166 137 recommended crystal spec ification for smd package parameter description range 1 range 2 range 3 unit fmin minimum frequency 8 14 28 mhz fmax maximum frequency 14 28 48 mhz r1 motional resistance (esr) 135 50 30 c0 shunt capacitance 4 4 2 pf cl parallel load capacitance 18 14 12 pf dl(max) maximum crystal drive level 300 300 300 w recommended crystal specific ation for thru-hole package parameter description range 1 range 2 range 3 unit fmin minimum frequency 8 14 24 mhz fmax maximum frequency 14 24 32 mhz r1 motional resistance (esr) 90 50 30 c0 shunt capacitance 7 7 7 pf cl parallel load capacitance 18 12 12 pf dl(max) maximum crystal drive level 1000 1000 1000 w [+] feedback
cy25403/cy25423/cy25483 document #: 001-12564 rev. *e page 8 of 12 test and measurement setup figure 4. test and measurement setup voltage and timing definitions figure 5. duty cycle definition figure 6. rise time = t rf , fall time = t rf 0.1 f v dd outputs c load gnd dut clock output v dd 50% of v dd 0v t 1 t 2 clock output t rf t rf v dd 80% of v dd 20% of v dd 0v [+] feedback
cy25403/cy25423/cy25483 document #: 001-12564 rev. *e page 9 of 12 ordering information some product offerings are factory programmed customer sp ecific devices with customized part numbers. the possible configurations table shows the available device types, but not co mplete part numbers. contact your local cypress fae of sales representative for more information possible configurations part number type package supply voltage production flow pb-free cy25403sxc field programmable 8-pin soic 2.5 v, 3.0 v, or 3.3 v commercial, 0c to 70c cy25403sxct field programmable 8-pin soic -tape and reel 2.5 v, 3.0 v, or 3.3 v commercial, 0c to 70c cy25423sxc field programmable 8-pin so ic 1.8 v commercial, 0c to 70c cy25423sxct field programmable 8-pin soic -t ape and reel 1.8 v commercial, 0c to 70c cy25483sxc field programmable 8-pin soic 2.5 v, 3.0 v, or 3.3 v commercial, 0c to 70c cy25483sxct field programmable 8-pin soic -tape and reel 2.5 v, 3.0 v, or 3.3 v commercial, 0c to 70c cy25403sxi field programmable 8-pin soic 2.5 v, 3.0 v, or 3.3 v industrial, -40c to +85c cy25403sxit field programmable 8-pin soic -tape and reel 2.5 v, 3.0 v, or 3.3 v industrial, -40c to +85c cy25423sxi field programmable 8-pin soic 1.8 v industrial, -40c to +85c cy25423sxit field programmable 8-pin soic -t ape and reel 1.8 v industrial, -40c to +85c cy25483sxi field programmable 8-pin soic 2.5 v, 3.0 v, or 3.3 v industrial, -40c to +85c cy25483sxit field programmable 8-pin soic -tape and reel 2.5 v, 3.0 v, or 3.3 v industrial, -40c to +85c programmer cy3675-clkmaker1 programming kit cy3675-soic8a socket adapter board, for programming cy25402, cy25403, cy25422, cy25423, cy25482, and cy25483 part number [ 1 ] type v dd (v) production flow pb-free cy25403sxc-xxx 8-pin soic supply voltage: 2.5 v, 3.0 v, or 3.3 v commercial, 0c to 70c cy25403sxc-xxxt 8-pin soic -tape and reel supply voltage: 2.5 v, 3.0 v, or 3.3 v commercial, 0c to 70c cy25403sxi-xxx 8-pin soic supply voltage: 2.5 v, 3.0 v, or 3.3 v industrial, -40c to +85c cy25403sxi-xxxt 8-pin soic -tape and reel supply voltage: 2.5 v, 3.0 v, or 3.3 v ind ustrial, -40c to +85c cy25423sxc-xxx 8-pin soic supply voltage: 1.8 v commercial, 0c to 70c cy25423sxc-xxxt 8-pin soic -tape and reel supp ly voltage: 1.8 v commercial, 0c to 70c CY25423SXI-XXX 8-pin soic supply voltage: 1.8 v industrial, -40c to +85c CY25423SXI-XXXt 8-pin soic -tape and reel supply voltage: 1.8 v industr ial, -40c to +85c cy25483sxc-xxx 8-pin soic supply voltage: 2.5 v, 3.0 v, or 3.3 v commercial, 0c to 70c cy25483sxc-xxxt 8-pin soic -tape and reel supply voltage: 2.5 v, 3.0 v, or 3.3 v commercial, 0c to 70c cy25483sxi-xxx 8-pin soic supply voltage: 2.5 v, 3.0 v, or 3.3 v industrial, -40c to +85c cy25483sxi-xxxt 8-pin soic -tape and reel supply voltage: 2.5 v, 3.0 v, or 3.3 v ind ustrial, -40c to +85c 1. xxx indicates factory programmed parts based on customer specif ic configuration. for more deta ils, contact your local cypress fae or sales representative. [+] feedback
cy25403/cy25423/cy25483 document #: 001-12564 rev. *e page 10 of 12 ordering code definitions package drawing and dimensions figure 7. 8-pin (150-mil) soic s8 package type: (t = tape and reel) customer specific identification code temperature code (c=commercial or i=industrial) 8-pin soic package marketing code: cy25403/23/83 = device number sx c/i - xxx t cy254x3 51-85066 *d [+] feedback
cy25403/cy25423/cy25483 document #: 001-12564 rev. *e page 11 of 12 acronyms acronym description dl drive level dnu do not use dut device under test emi electromagnetic interference esd electrostatic discharge fae field application engineer fs frequency select jedec eia joint electron devices engineering council electronic industries alliance lvcmos low voltage complemetary metal oxide semiconductor oe output enable osc oscillator pd power down pll phase locked loop ppm parts per million ss spread spectrum ssc spread spectrum clock sson spread spectrum on [+] feedback
document #: 001-12564 rev. *e revised june 02, 2010 page 12 of 12 all products and company names mentioned in this document may be the trademarks of their respective holders. cy25403/cy25423/cy25483 ? cypress semiconductor corporation, 2007-2010. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 document title: cy25403/cy25423/cy25483 three pll pr ogrammable clock generator with spread spectrum document number: 001-12564 rev. ecn no. issue date orig. of change description of change ** 690296 see ecn rgl new data sheet *a 815788 see ecn rgl minor change: to post on web *b 1428744 see ecn rgl/aesa changed data sheet fo rmat to match generic part, cy2544/46 added new device and specification for high ref. input voltage part, cy25483 removed preliminary from title page replaced clk2 with refout *c 2748211 08/10/09 tsai posting to external web. *d 2899300 03/25/10 cxq updated ordering informati on. added note regarding possible configura- tions in ordering information section. added possible configurations table for ?xxx? parts. updated package drawing and dimensions *e 2898568 06/02/10 cxq updated ordering information and template. [+] feedback

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